50-250 MHz ΔΣ DLL for Clock Synchronization.

San-Jeow Cheng Lin Qiu Yuanjin Zheng Chun-Huat Heng

Published in: IEEE J. Solid State Circuits (2010)

Keyphrases

high speed
fpga device
power consumption
clock frequency
low power
music score
chaotic systems
phase locked
real time
wavelet transform
high frequency
hardware implementation
max sat
chaotic neural network