C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.
Jin Guo
Antonis Papanikolaou
H. Zhang
Francky Catthoor
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2007)
Keyphrases
</>
physical design
design methodology
design tools
query optimization
high speed
chip design
database administrators
database
design process
neural network
management system
object oriented
decision making
fuzzy neural network
power dissipation