Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability.
P. V. SrideviPublished in: J. Circuits Syst. Comput. (2021)
Keyphrases
- low power
- power consumption
- single chip
- low cost
- vlsi architecture
- low power consumption
- logic circuits
- high speed
- cmos technology
- power reduction
- power dissipation
- digital signal processing
- gate array
- high power
- wireless transmission
- nm technology
- analog to digital converter
- image processing
- design process
- mixed signal
- vlsi circuits
- cmos image sensor