Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder.

Ya-Cheng Lu Erl-Huei Lu

Published in: IEICE Trans. Commun. (2010)

Keyphrases

hardware implementation
fpga implementation
computational complexity
search space
low latency
motion estimation
data sets
high speed
low complexity
efficient implementation
highly efficient
image processing algorithms