Low Power and Suppressed Noise 6T, 7T SRAM Cell Using 18 nm FinFET.
T. Santosh KumarSuman Lata TripathiPublished in: Wirel. Pers. Commun. (2023)
Keyphrases
- low power
- power consumption
- cmos technology
- low cost
- high speed
- power reduction
- nm technology
- single chip
- high power
- vlsi circuits
- wireless transmission
- vlsi architecture
- low power consumption
- logic circuits
- noise level
- digital signal processing
- energy dissipation
- mixed signal
- image sensor
- signal to noise ratio
- low voltage
- noise model
- power management
- power dissipation
- gate array
- power saving