Model Checking on Trees with Path Equivalences.
Rajeev AlurPavol CernýSwarat ChaudhuriPublished in: TACAS (2007)
Keyphrases
- model checking
- temporal logic
- formal verification
- finite state
- model checker
- automated verification
- symbolic model checking
- verification method
- temporal properties
- formal specification
- finite state machines
- partial order reduction
- transition systems
- bounded model checking
- timed automata
- computation tree logic
- pspace complete
- concurrent systems
- process algebra
- reachability analysis
- epistemic logic
- asynchronous circuits
- tree automata
- distributed systems
- deterministic finite automaton