FPGA Low Power Technology Mapping for Reuse Module Design under the Time Constraint.
Jae-Jin KimHyeon-Mi YangKeun Ho RyuHi-Seok KimPublished in: FGCN (2) (2008)
Keyphrases
- low power
- gate array
- single chip
- low power consumption
- power consumption
- high speed
- low cost
- cmos technology
- logic circuits
- digital signal processing
- verilog hdl
- ultra low power
- nm technology
- vlsi architecture
- cmos image sensor
- power reduction
- wireless transmission
- power dissipation
- real time
- high power
- mixed signal
- software systems