Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions.
J. A. LópezGinés DoménechR. RuizTom J. KazmierskiPublished in: ISCAS (4) (2002)
Keyphrases
- building blocks
- neural network
- high level synthesis
- hardware implementation
- parallel architecture
- adaptive resonance theory
- hardware design
- pattern recognition
- low cost
- image processing
- circuit design
- hardware description language
- fpga implementation
- software components
- field programmable gate array
- real time
- signal processing
- artificial neural networks
- integrated circuit
- image segmentation
- case study
- databases