Hardware Simulator of Reduction-Based Parallel Inference Machine PIM-R.
Mamoru SugieM. YoneyamaT. SakabeM. IwasakiS. YoshizumiMoritoshi AsoHajime ShimizuRikio OnaiPublished in: LP (1985)
Keyphrases
- parallel hardware
- massively parallel
- low cost
- multi core processors
- computer architecture
- parallel architectures
- parallel processing
- parallel execution
- hardware and software
- high end
- bayesian networks
- digital computer
- identical machines
- parallel machines
- hardware implementation
- probabilistic inference
- parallel implementation
- real time
- processing units
- parallel computation
- bayesian inference
- hardware architecture
- data acquisition
- test bed
- simulation model
- computational power
- personal computer
- multithreading
- batch processing
- parallel processors
- commodity hardware
- parallel programming
- shared memory
- single instruction multiple data