Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs.
Ameer M. S. AbdelhadiHe LiPublished in: FPL (2021)
Keyphrases
- field programmable gate array
- hardware implementation
- parallel computing
- embedded systems
- programmable logic
- hardware design
- computing systems
- image processing algorithms
- fpga implementation
- hardware software
- fpga technology
- application specific integrated circuits
- neural network
- reconfigurable hardware
- parallel architectures
- chaotic systems
- asynchronous circuits
- processing elements
- search engine
- concurrent programs
- learning algorithm
- general purpose processors
- data mining