FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm.

Vikram Arkalgud Chandrasetty Syed Mahfuzul Aziz

Published in: J. Networks (2011)

Keyphrases

fpga implementation
message passing
reduced complexity
sum product algorithm
dynamic programming
ldpc codes
computational complexity
distributed systems
hardware implementation
probabilistic model
matching algorithm
computer vision
similarity measure
low density parity check