An optimum ADC output word length selection for low power communication architectures.

N. Alivelu Manga M. Madhavi Latha

Published in: ICACCI (2013)

Keyphrases

low power
low cost
single chip
high speed
power consumption
high power
vlsi architecture
cmos technology
digital signal processing
wireless transmission
logic circuits
low power consumption
image sensor
mixed signal
communication networks
signal processor
power reduction
delay insensitive
gate array