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A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise.
Dongin Kim
SeongHwan Cho
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
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low power
low cost
high speed
power consumption
vlsi architecture
single chip
wireless transmission
logic circuits
vlsi circuits
high power
low power consumption
digital signal processing
cmos technology
delay insensitive
ultra low power
real time
power reduction
mixed signal
image compression