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A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells.
Mina Kim
Seojin Choi
Jaehyouk Choi
Published in:
VLSIC (2015)
Keyphrases
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computationally efficient
load balancing
end to end delay
feature selection
neural network
multiscale
high resolution
low resolution
power consumption
fault tolerance
hardware implementation