Login / Signup
An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors.
Cheol Hong Kim
Sung Woo Chung
Chu Shik Jhon
Published in:
IEICE Trans. Inf. Syst. (2006)
Keyphrases
</>
embedded processors
memory hierarchy
single chip
parallel implementation
hardware and software
instruction set
wireless sensor networks
energy efficient
image sequences
low cost
memory access
real time
image processing
response time
energy consumption