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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V.
Christopher Celio
Daniel Palmer Dabbelt
David A. Patterson
Krste Asanovic
Published in:
CoRR (2016)
Keyphrases
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instruction set
computer architecture
instruction set architecture
application specific
floating point
computer systems
embedded systems
memory subsystem
parallel computing
level parallelism
ibm power processor
real time
artificial intelligence
nearest neighbor
operating system
memory access