Automated Field-based Decomposition to Accelerate Model Checking FPGA-based TCP/IP.
Tianqi FangLisong XuWitawas Srisa-anPublished in: ICC (2020)
Keyphrases
- model checking
- tcp ip
- temporal logic
- formal verification
- automated verification
- temporal properties
- model checker
- symbolic model checking
- formal specification
- computation tree logic
- reachability analysis
- formal methods
- verification method
- ip networks
- bounded model checking
- transition systems
- concurrent systems
- epistemic logic
- timed automata
- pspace complete
- internet protocol
- computer networks
- web services
- multi agent
- smart card
- linear temporal logic
- planning domains
- modal logic
- reactive systems
- hardware implementation
- binary decision diagrams