A Multi-Pixel Compression for Low-Power Imaging System and Architecture.
Wonseok LeeKyeongjong LimJeonghyeon CheonSoyi JeongJinyeon LimYoungsung ChoShusaku IshikawaSeongwon JoSeongwook SongMinsu KangKyungil KimSeunghyun LimYoungjin KimSunghoo ChoiJungchan KyoungPublished in: ISCAS (2023)
Keyphrases
- low power
- vlsi architecture
- power consumption
- low cost
- high speed
- image sensor
- mixed signal
- cmos technology
- single chip
- high power
- logic circuits
- nm technology
- digital signal processing
- image compression
- low power consumption
- wireless transmission
- analog to digital converter
- vlsi circuits
- real time
- cmos image sensor
- gate array
- vlsi implementation
- compression algorithm