A new parallel architecture for low power linear feedback shift registers.
Abdullah MamunRajendra S. KattiPublished in: ISCAS (2) (2004)
Keyphrases
- low power
- parallel architecture
- power consumption
- low cost
- high speed
- parallel processing
- single chip
- hardware implementation
- systolic array
- shared memory
- high power
- digital signal processing
- vlsi architecture
- vlsi circuits
- wireless transmission
- high level synthesis
- gate array
- parallel implementation
- logic circuits
- distributed memory
- low power consumption
- message passing
- computational complexity
- cmos technology
- real time
- power reduction
- mixed signal
- application specific
- image sequences