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A novel FPGA architectural implementation of pipelined thinning algorithm.
Pei-Yung Hsiao
Chun-Ho Hua
Chien-Chen Lin
Published in:
ISCAS (2) (2004)
Keyphrases
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thinning algorithm
parallel architecture
hardware implementation
rotation invariant
endpoints
hardware architecture
topology preserving
image processing
binary images
efficient implementation
discrete geometry
computer vision
feature vectors
gray level
character recognition
binary pictures