On the Exploration of Connection-aware Partitioning for Parallel FPGA Routing.
Yun ZhouDries VercruyceDirk StroobandtPublished in: FPGA (2020)
Keyphrases
- parallel hardware
- load balance
- parallel implementation
- pipelined architecture
- partitioning algorithm
- low cost
- systolic array
- real time image processing
- parallel architecture
- field programmable gate array
- shared memory
- high speed
- shortest path
- parallel processing
- hardware implementation
- real time
- routing protocol
- ad hoc networks
- data partitioning
- parallel computing
- hardware design
- interconnection networks
- load balancing
- fpga implementation
- routing algorithm
- routing problem
- fpga hardware
- verilog hdl