A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology.

Hechen Wang Fa Foster Dai

Published in: ESSCIRC (2017)

Keyphrases

cmos technology
spl times
low power
low voltage
power consumption
parallel processing
random access memory
high speed
silicon on insulator
power dissipation
low cost
flip flops
high resolution
image sensor
video sequences
mixed signal
high quality
digital images
pattern recognition
computer vision