A fast hierarchical arbitration scheme for multi-tb/s packet switches with shared memory switching.
Daniel PopaGeorg PostLudovic NoiriePublished in: Bell Labs Tech. J. (2009)
Keyphrases
- shared memory
- parallel architecture
- message passing
- parallel algorithm
- distributed memory
- parallel tree search
- parallel computing
- parallel programming
- parallel machines
- parallel architectures
- parallel computers
- multi processor
- address space
- high quality
- packet size
- heterogeneous platforms
- shared memory multiprocessors