Login / Signup
A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming.
Myung-Jun Choe
Bang-Sup Song
Kantilal Bacrania
Published in:
IEEE J. Solid State Circuits (2000)
Keyphrases
</>
analog to digital converter
high speed
low power
foreground objects
low cost
power consumption
single chip
vlsi circuits
delay insensitive
image processing
analog vlsi
background noise
protein folding
data flow
background model
low voltage
image processing algorithms
moving objects
real time