A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.
Cong LiuWeiwei ShenTianlong MaYibo FanXiaoyang ZengPublished in: ASICON (2013)
Keyphrases
- mode decision
- intra prediction
- block size
- variable block size
- video coding standard
- complexity reduction
- video compression
- macroblock
- spatial correlation
- coding efficiency
- bit rate
- intra coding
- low complexity
- pixel wise
- rate distortion
- motion vectors
- motion estimation
- video transmission
- quadtree
- inter frame
- video quality
- image coding
- video coding
- motion compensation
- real time
- bitstream
- image data