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High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation.
Myeongjin Kim
Eui-Young Chung
Sungroh Yoon
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2009)
Keyphrases
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high speed
quasi static
simulation model
frame rate
graph cuts
loss function
power consumption