SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation.

Hyeyeong Lee Joonhyung Kim Jongsun Park

Published in: ISOCC (2022)

Keyphrases

low latency
high speed
shift register
random access memory
low power
low voltage
high bandwidth
high throughput
highly efficient
power reduction
power consumption
real time
massive scale
cmos technology
stream processing
data transmission
virtual machine
low complexity
motion estimation
data sets