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A 9.96 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture.
Carlo Condo
Pascal Giard
François Leduc-Primeau
Gabi Sarkis
Warren J. Gross
Published in:
CoRR (2016)
Keyphrases
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low complexity
multiple description coding
video coding scheme
vlsi architecture
distributed video coding
video encoder
reed solomon codes
wyner ziv
motion estimation
multiple description
turbo codes
computational complexity
joint source channel
error resilience
rate allocation
error resilient
video streaming
packet loss
transmission scheme
bit plane
mode decision
video coding
scalable video
bit errors
forward error correction
low bit rate