A 9.96 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture.
Carlo CondoPascal GiardFrançois Leduc-PrimeauGabi SarkisWarren J. GrossPublished in: CoRR (2016)
Keyphrases
- low complexity
- multiple description coding
- video coding scheme
- vlsi architecture
- distributed video coding
- video encoder
- reed solomon codes
- wyner ziv
- motion estimation
- multiple description
- turbo codes
- computational complexity
- joint source channel
- error resilience
- rate allocation
- error resilient
- video streaming
- packet loss
- transmission scheme
- bit plane
- mode decision
- video coding
- scalable video
- bit errors
- forward error correction
- low bit rate