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A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes.
Cheng-Ze Shao
Shih-Che Kuo
Yu-Te Liao
Published in:
IEEE J. Solid State Circuits (2021)
Keyphrases
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low voltage
power supply
low power
analog vlsi
low cost
power system
user feedback
vlsi circuits
high voltage
random access memory
relevance feedback
real time
reference frame
power consumption
high speed
feedback mechanisms
delay insensitive
relational databases
database