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FPGA implementation of AES algorithm for high throughput using folded parallel architecture.
K. Rahimunnisa
P. Karthigaikumar
Soumiya Rasheed
J. Jayakumar
S. Suresh Kumar
Published in:
Secur. Commun. Networks (2014)
Keyphrases
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high throughput
fpga implementation
hardware implementation
parallel architecture
dynamic programming
higher order
real time
computer vision
high speed
microarray
parallel implementation
data mining
image analysis
np hard
energy function