Buffer-aware Worst Case Timing Analysis of Wormhole Network On Chip.

Ahlem Mifdaoui Hamid Ayed

Published in: CoRR (2016)

Keyphrases

network on chip
worst case
routing algorithm
network simulator
upper bound
mobile ad hoc networks
lower bound
multi processor
data transfer
ad hoc networks
computational complexity
interconnection networks
end to end
np hard
fault tolerant
power dissipation
routing protocol
high speed
web services