An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm.
Nandireddygari Ramya TejaS. ArunmethaSrinivas BachuPublished in: Concurr. Comput. Pract. Exp. (2021)
Keyphrases
- hardware architecture
- field programmable gate array
- hardware implementation
- pipelined architecture
- parallel computing
- parallel architectures
- processing elements
- motion estimation
- genetic algorithm
- embedded systems
- fpga device
- programmable logic
- hardware architectures
- massively parallel
- efficient implementation
- computing systems
- parallel programming
- digital signal processors
- neural network
- reconfigurable hardware
- artificial neural networks
- xilinx virtex
- object oriented
- pattern recognition
- pairwise
- signal processing
- associative memory