Synthesis of Hardware Simulators for Use in Model Checking.
Dominique GückelPublished in: AlgoSyn (2010)
Keyphrases
- model checking
- temporal logic
- formal verification
- finite state
- model checker
- formal specification
- automated verification
- verification method
- partial order reduction
- finite state machines
- reachability analysis
- transition systems
- symbolic model checking
- temporal properties
- timed automata
- bounded model checking
- epistemic logic
- pspace complete
- concurrent systems
- asynchronous circuits
- embedded systems
- deterministic finite automaton
- rough sets
- reactive systems
- search algorithm
- partial observability
- formal methods
- partial order
- abstract interpretation
- ctl model update