A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding.
Paris KitsosNikolaos S. VorosTasos DagiuklasAthanassios N. SkodrasPublished in: DSP (2013)
Keyphrases
- high definition
- high speed
- video coding
- fpga implementation
- video communication
- video compression
- bit rate
- motion estimation
- hardware implementation
- rate distortion
- motion compensation
- motion compensated
- video quality
- real time
- motion vectors
- mpeg avc
- rate control
- macroblock
- field programmable gate array
- video codec
- image quality
- compression efficiency
- video coding standard
- video encoder
- image processing algorithms
- scalable video coding
- video coder
- error resilience
- low cost
- computational complexity
- bit allocation
- three dimensional
- frame rate
- low bit rate
- video conferencing
- bitstream
- motion field
- spatial domain