Hardware implementation aspects of a detector based on successive interference cancellation in a DS/CDMA system.
Thomas OlssonCarl Magnus JönssonViktor ÖwallPeter NilssonPublished in: PIMRC (1998)
Keyphrases
- hardware implementation
- efficient implementation
- signal processing
- hardware design
- software implementation
- dedicated hardware
- image processing algorithms
- fpga implementation
- neural network
- hardware architecture
- field programmable gate array
- pipeline architecture
- parallel architecture
- memory management
- multipath
- pattern recognition
- image binarization
- shift register
- pipelined architecture
- processing elements
- high speed
- feature extraction
- information systems
- data mining