Towards a metrics suite for evaluating cache side-channel vulnerability: Case studies on an open-source RISC-V processor.
Pengfei GuoYingjian YanJunjie WangJingxin ZhongYanjiang LiuJinsong XuPublished in: Comput. Secur. (2023)
Keyphrases
- open source
- case study
- instruction set
- memory subsystem
- open source software
- processor core
- application specific
- source code
- embedded processors
- memory access
- cache misses
- memory hierarchy
- computation intensive
- multithreading
- prefetching
- multiprocessor systems
- shared memory multiprocessors
- countermeasures
- single chip
- real world
- query processing
- main memory
- shared memory multiprocessor
- database workloads
- lessons learned
- high speed
- embedded systems
- development process
- hit rate
- smart card
- power consumption
- industry standard
- data access
- parallel processing
- real time