Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.

Ireneusz Brzozowski Andrzej Kos

Published in: PATMOS (2005)

Keyphrases

input vectors
power dissipation
power reduction
power consumption
low power
input vector
cmos technology
feature space
feed forward neural networks
machine learning
pattern recognition
multilayer perceptron
logic circuits
vector quantizer
reduced set
pattern matching