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Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations.

Mohsen RajiBehnam Ghavami
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
  • error rate
  • test set
  • rule sets
  • pattern recognition
  • asynchronous circuits
  • machine learning
  • lower bound
  • lower error rates
  • false discovery rate