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Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.

José Luis NevesEby G. Friedman
Published in: J. VLSI Signal Process. (1997)
Keyphrases
  • high speed
  • power consumption
  • information systems
  • scheduling problem
  • process model
  • tree structure
  • decision making
  • image sequences
  • r tree