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A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC.

Young-Ju KimHee-Cheol ChoiPil-Seon YooDong-Suk LeeJoong-Ho ChoiSeung-Hoon Lee
Published in: APCCAS (2008)
Keyphrases
  • high speed
  • power consumption
  • high levels
  • single chip
  • real time
  • real world
  • analog to digital converter
  • machine learning
  • artificial intelligence
  • artificial neural networks
  • simulation model
  • low power