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Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented QC-LDPC Decoders.

Zhen GaoYinghao ChengPedro Reviriego
Published in: DFT (2022)
Keyphrases
  • real time
  • low cost
  • hardware implementation
  • error correction
  • high speed
  • image quality
  • associative memory
  • evaluation method
  • fpga device