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Power, performance, and area evaluation across 180nm-28nm technology nodes based on benchmark circuits.
Minghui Yin
Zhiqiang Li
Weihua Zhang
Hongwei Liu
Huanhuan Zhou
Yunxia You
Chen Wang
Published in:
IEICE Electron. Express (2024)
Keyphrases
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nm technology
power dissipation
power consumption
low power
cmos technology
power reduction
power management
digital signal processing
directed graph
power saving
clock gating
logic circuits
analog circuits
finite state machines
delay insensitive
real time
signal processing
high speed
quantitative evaluation
efficient implementation
parallel processing
shortest path
low cost
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