An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA.
Xiaodi YinZhipeng WuDejian LiChongfei ShenYu LiuPublished in: IEEE Embed. Syst. Lett. (2024)
Keyphrases
- field programmable gate array
- convolutional neural networks
- hardware implementation
- embedded systems
- hardware architecture
- hardware design
- image processing algorithms
- fpga implementation
- low cost
- programmable logic
- real time
- parallel computing
- convolutional network
- computing systems
- parallel hardware
- software implementation
- low power consumption
- dedicated hardware
- high speed
- massively parallel
- data acquisition
- fpga technology
- single chip
- high dimensional
- hardware software
- reconfigurable hardware
- hardware software co design
- high end
- sparse data
- parallel implementation
- hardware and software
- parallel architectures
- fpga device
- efficient implementation
- general purpose processors
- computer systems
- parallel architecture
- hardware architectures
- sparse representation
- image processing