Low Power Optimized Array Multiplier with Reduced Area.

Padma Devi Gurinder Pal Singh Balwinder Singh

Published in: HPAGC (2011)

Keyphrases

low power
power consumption
high speed
low cost
image sensor
wireless transmission
low power consumption
single chip
vlsi architecture
vlsi circuits
digital signal processing
high power
gate array
logic circuits
floating point
power reduction
cmos technology
digital camera