Login / Signup

Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA.

Mahabub Hasan MahalatNikhil UgaleRohit ShahareBibhash Sen
Published in: VLSI-SoC (2018)
Keyphrases
  • high speed
  • single chip
  • case study
  • hardware design
  • power reduction
  • power consumption
  • low power
  • feedback loop
  • low power consumption
  • fpga technology
  • verilog hdl