Hardware implementation of a soft cancellation decoder for polar codes.
Guillaume BerhaultCamille LerouxChristophe JégoDominique DalletPublished in: DASIP (2015)
Keyphrases
- hardware implementation
- fpga implementation
- error control
- reed solomon
- decoding algorithm
- error correction
- joint source channel
- signal processing
- low density parity check
- ldpc codes
- efficient implementation
- hardware design
- field programmable gate array
- turbo codes
- low complexity
- image processing algorithms
- software implementation
- rotation invariant
- hardware architecture
- dedicated hardware
- memory management
- frequency domain
- error concealment
- rate allocation
- distributed video coding
- fpga device
- parallel architecture
- real time
- image binarization
- pipeline architecture
- machine learning
- pipelined architecture
- rate compatible punctured convolutional
- channel coding
- message passing
- neural network