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A 15-MHz Bandwidth 1-0 MASH Σ Δ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR.
Seung-Chul Lee
Yun Chiu
Published in:
IEEE J. Solid State Circuits (2014)
Keyphrases
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error analysis
nonlinear optimization
camera calibration
computational power
high speed
memory usage
taylor series expansion
memory requirements
storage capacity
error rate
video streaming
computing power
network bandwidth
auto associative
measurement error