Login / Signup

A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INLpp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links.

Zhaowen WangPeter R. Kinget
Published in: ISSCC (2022)
Keyphrases
  • high speed
  • data sets
  • noisy data
  • real time
  • training data
  • low cost
  • missing data
  • data analysis
  • low power
  • data sources
  • input data
  • frequency band