The design of a low-power low-noise phase lock loop.
Abishek MannAmit KaralkarLili HeMorris JonesPublished in: ISQED (2010)
Keyphrases
- low power
- low power consumption
- low cost
- power consumption
- single chip
- high speed
- logic circuits
- vlsi architecture
- power reduction
- gate array
- digital signal processing
- real time
- high power
- cmos technology
- power dissipation
- design process
- mixed signal
- wireless transmission
- vlsi circuits
- ultra low power
- design considerations
- noise model
- general purpose
- image processing