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High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.
Minh Quang Do
Per Larsson-Edefors
Mindaugas Drazdziulis
Published in:
DSD (2007)
Keyphrases
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power consumption
high accuracy
nm technology
low power
neural network
higher level
conceptual model
estimation algorithm
cmos technology
power reduction
process model
software architecture
estimation error
design considerations
process management